1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device having a silicide film.
2. Description of the Background Art
In recent years, high integration of semiconductor devices has been improved and a large number of elements are mounted in a single chip. Most of these elements are MOS transistors that can be classified into an nMOS transistor through which electrons pass (i.e., the negative MOS transistor) and a pMOS transistor through which holes pass (i.e., the positive MOS transistor). In a semiconductor device, such transistors having different poralities are combined to configure a circuit.
In a conventional MOS transistor, to lower the resistances of a source/drain region and gate electrode, a silicide film is formed thereon. The silicide film is generally formed by directly making the source/drain region and gate electrode into silicide. When making the gate electrode into silicide, a gate insulating film is formed therebelow and thus it is avoided that silicide formation reaction extends through the gate insulating film to a semiconductor substrate. On the other hand, when making the source/drain region into silicide, silicide formation reaction extends in the direction of the depth of the semiconductor substrate. It is therefore necessary to prevent an increase in junction leakage by setting the depth of the source/drain region so as be sufficiently large. This is one obstacle to the miniaturization of semiconductor devices.
To overcome the above problem, in Japanese Patent Application Laid-Open No. 11-11980 (hereinafter, referred to as “patent documents 1”), a technique of miniaturizing a semiconductor device is suggested. That is, a suppression atom for suppressing silicide formation reaction (hereinafter referred to simply as a “suppression atom”) is introduced into a source/drain region such that a silicide film of the source/drain region is thinner than a silicide film of a gate electrode.
In this technique, fluorine atom, nitrogen atom, or oxygen atom is used as a suppression atom, and the atom is introduced into the vicinity of the surface of the source/drain region, thereby suppressing silicide formation reaction in the source/drain region.
Meanwhile, in Japanese Patent Application Laid-Open No. 2001-53027, such a technique is suggested, in which with the aim of lowering the resistance of a source/drain region, a silicon germanium (SiGe) layer is formed on the source/drain region and the silicon germanium layer is made into silicide.
In the conventional technique suggested in the patent documents 1, the suppression atom is introduced into the vicinity of the surface of the source/drain region, and then the entire region where the suppression atom has been introduced is made into silicide (see FIGS. 1 and 8 in the patent documents 1). Therefore, silicide formation reaction extends locally in the direction of the depth of the semiconductor substrate, and silicide is formed up to the vicinity of a junction. As the result, junction leakage increases in some cases. Following is a concrete description of this problem.
For example, by anneal at about 500° C., cobalt (Co) that is refractory metal and often used for silicide formation reaction becomes a silicon metal compound in which CoSi and Co2Si are mixed. Cobalt monosilicide in which a cobalt atom is combined with one silicon atom, such as CoSi and Co2Si, is high in resistance. Therefore, a further anneal at a temperature of not less than 700° C. is normally performed to subject the cobalt monosilicide to a phase transition for obtaining CoSi2 that has a lower resistance.
The reaction process through which the monosilicide such as CoSi or Co2Si changes to CoSi2 requires more silicon. CoSi and Co2Si require different numbers of silicon atoms necessary for changing into CoSi2, thus causing a difference in reaction rate. Therefore, the sizes of silicide grains of CoSi2 differ depending on the type of the monosilicide and how the adjacent silicide grows. As the result, when monosilicide is surrounded by grains that grow quickly, the supply of silicon is effected locally only in one direction of the substrate, and silicide formation reaction extends deeply in the semiconductor substrate so that silicide grows up to the vicinity of a junction in some cases.
Although, in the technique described in the patent documents 1, the silicide formation reaction is suppressed by the introduced nitrogen atom etc., the entire region where the suppression atom has been introduced is finally made into silicide. Therefore, no suppression atom is present below the region to be made into silicide. From the reason described above, the silicide formation reaction extends locally to the underside of the region to be made into silicide, which may increase junction leakage.
Recently, as the miniaturization of semiconductor devices is improved, a silicon layer of an SOI (silicon on insulator) substrate is being thinner and the difference between a silicide film and silicon layer is being reduced. Accordingly, when a source/drain region formed in the silicon layer of the SOI substrate is made into silicide, silicide grows greatly toward a channel region underlying a gate electrode at which there is more silicon than the underside of a region to be made into silicide. This may increase the leakage current between source and drain.
Even if the technique in the patent documents 1 is applied to an SOI substrate, the same problem occurs when the source/drain region is made into silicide from its upper surface, because the suppression atom is introduced only to the underside of an exposed surface of the source/drain region.